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Final Data Sheet, Rev. 1.0, February 2009
TLE 8203E
Mirror Power IC
Automotive Power
TLE 8203E
Table of Contents
Table of Contents
1 2 3 3.1 3.2 4 4.1 4.2 4.3 5 5.1 5.2 5.3 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 7.5 7.6 8 8.1 8.2 9 9.1 9.2 10 10.1 10.2 11 11.1 12 12.1 13 14 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 8 8
Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Address Selection and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 11 11 12 12 12 13 15 17 17
Power-Outputs 4-6 (Bridge Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power-Output 7 (Mirror Heater Driver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-Outputs 8 and 10 (Lamp drivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Logic In- and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Final Data Sheet
2
Rev. 1.0, 2009-02-04
Mirror Power IC TLE 8203E
TLE 8203E
1
Features * * * * * * * * * * * * * * *
Overview
Three half-bridges ( 1 x 0.7 ; 2 x 1.3 RDSON(MAX) @ TJ=150C ) for mirror position High-side switch ( 0.17 RDSON(MAX) @ TJ=150C ) for mirror defrost Two high-side switches ( 0.8 RDSON(MAX) @ TJ=150C ) for 5 W and 10 W lamps Current sense analog output with multiplexer All outputs with short circuit protection and diagnosis Over-temperature protection with warning Open load diagnosis for all outputs Charge pump-Output for n-channel MOSFET reverse-polarity protection Very low current consumption in sleep mode Standard 16-bit SPI for control and diagnosis Over- and Under-voltage Lockout DSO package with exposed pad for low thermal resistance Part of scalable door family products Green Product (RoHS compliant) AEC Qualified
PG-DSO-36-50
Functional Description The TLE 8203E is an Application Specific Standard Product for automotive mirror control applications. It includes the power stages necessary to drive mirror loads such as mirror position, mirror defrost and 5W or 10W lamp, i.e. turn signal. It is a monolithic die based on Infineon's smart mixed technology SPT which combines bipolar and CMOS control circuitry with DMOS power devices. The short circuit and over-temperature protection and detailed diagnosis offered meet the automotive application safety requirements. The current sense output mprove system reliability and performance. The standard SPI interface saves microcontroller I/O lines while still providing flexible control of the power stages and a detailed diagnosis.
Type TLE 8203E Final Data Sheet
Package PG-DSO-36-50 3
Marking TLE8203E Rev. 0.9, 2009-01-23
TLE 8203E
Block Diagram
2
Block Diagram
Vs
GO CP Chargepump RevPol MOS driver FaultDetect
Vcc INH CSN CLK DI DO PWM1 PWM2 ISO
Biasing
OUT4
OUT5
SPI OUT6 Logic IN current sense MUX Logic and Latch OUT7
OUT8 OUT10
GND
Figure 1 Block Diagram
Final Data Sheet
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Rev. 1.0, 2009-02-04
TLE 8203E
Pin Configuration
3
3.1
Pin Configuration
Pin Assignment
Figure 2
Pin Configuration PG-DSO-36-50
3.2
Pin
Pin Definitions and Functions
Symbol Function Cooling Tab; internally connected to GND; To reduce thermal resistance, place cooling areas and thermal vias on PCB. Ground; internally connected to cooling tab (exposed pad). Power-Output of Half-Bridge output 5; DMOS half-bridge (mirror position). Power-Output of Half-Bridge output 6; DMOS half-bridge (mirror position). Power Supply; needs decoupling capacitors to GND. > 47 F electrolytic in parallel with 100 nF ceramic is recommended. All VS pins must be connected externally. Inhibit; active low. Sets the device in sleep mode with low current consumption when left open or pulled to LOW. Has an internal pull-down current source. Logic Input for Direct Power Stage Control; direct input to control the high-side switches selected by the SPI xsel1 bits in control register CtrlReg01. Logic Input for Direct Power Stage Control; direct input to control the switches selected by the SPI xsel2 bits in control register CtrlReg11. 5 Rev. 1.0, 2009-02-04
cooling GND tab 1, 18, 19, 36 2 3 4, 26, 30, 33 5 6 7 GND OUT5 OUT6
VS
INH PWM1 PWM2
Final Data Sheet
TLE 8203E
Pin Configuration Pin 8 9 10 Symbol ISO Function Current Sense Output; Mirrors the current of the high-side switch selected by the current sense multiplexer control bits ISx. Logic Supply Voltage; needs decoupling capacitors to GND (pin 1). 10 F electrolytic in parallel with 10 nF ceramic is recommended. Serial Data Output; Transfers data to the master when the chip is selected by CSN = LOW. Data transmission is synchronized by CLK, DO state is changed on the rising edge of CLK. The most significant bit (MSB) is transferred first. The pin is tristated as long as CSN = HIGH. Serial Data Clock Input; Receives the clock signal from the master and clocks the SPI shift register. Has an internal pull-down current source. Serial Port Chip Select Not Input; SPI communication is enabled by pulling CSN to LOW. CLK must be LOW during the transition of CSN. The CSN-pin has an internal pull-up current source. Serial Data Input; Receives serial data from the master when the chip is selected by CSN = LOW. Data transmission is synchronized by CLK. Data are accepted on the falling edge of CLK. The LSB is transferred first. The DI-pin has an internal pull-down current source. Gate Out; Charge pump output to drive the gate of external n-channel MOSFET for reverse polarity protection. Not Connected Not Connected Not Connected Not Connected Power-Output of High-Side Switch output 10; DMOS high-side switch (lamp driver Charge Pump; pin for optional external charge-pump reservoir capacitor. 3.3 nF to VS is recommended. Not Connected Power-Output of High-Side Switch output 8; DMOS high-side switch (lamp driver) Power Output of High-Side Switch output 7; DMOS high-side switch (mirror heat) Power-Output of Half-Bridge output 4; DMOS half-bridge (sum of mirror position). Not Connected
VDD
DO
11 12
CLK CSN
13
DI
14 15, 16 20, 21 22 24 25 27 28 29 31, 32 34 35
GO N.C N.C N.C N.C OUT10 CP N.C OUT8 OUT7 OUT4 N.C.
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TLE 8203E
General Product Characteristics
4 4.1
General Product Characteristics Absolute Maximum Ratings
Absolute Maximum Ratings 1) Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Voltages 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 Supply voltage Logic supply voltage Logic input- and output voltages Voltage at GO-pin Junction Temperature Storage Temperature ESD capability of power stage output and VS pins vers. GND Parameter Symbol Limit Values Min. Max. 40 5.5 5.5 V V V V C C kV kV - - - - - -
2)
Unit
Conditions
VS VDD VGO Tj Tstg VESD
-0.3 -0.3 -0.3 -16 -40 -50 - -
VS + 5
150 150 4 2
Temperatures
ESD Susceptibility
ESD capability of logic pins and ISO pin VESD vers. GND
2)
1) Not subject to production test, specified by design. 2) Human Body Model according to JEDEC EIA/JESD22-A114-B (1.5k, 100 pF)
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation.
Final Data Sheet
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Rev. 1.0, 2009-02-04
TLE 8203E
General Product Characteristics
4.2
Pos. 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6
Operating Range
Parameter Supply voltage range for normal operation Extended supply voltage range for operation Logic supply voltage range for normal operation Extended logic supply voltage range for operation SPI clock frequency Junction temperature Symbol Limit Values Min. Max. 20 40 5.25 5.5 2 150 V V V V MHz C - (Limit Values Deviations possible) - (Limit Values Deviations possible) - - 8 5 4.75 4.75 - -40 Unit Conditions
VS VS(ext) VDD VDD(ext) fCLK Tj
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Pos. 4.3.1 4.3.2
Thermal Resistance
Parameter Junction to Case Junction to Ambient Symbol Min. Limit Values Typ. 5 25 Max. - - K/W K/W
1) 1) 2)
Unit
Conditions
RthjC RthjA
- -
1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer
Final Data Sheet
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Rev. 1.0, 2009-02-04
TLE 8203E
Monitoring Functions
5
5.1
*
Monitoring Functions
Power Supply Monitoring
The power supply Voltage VS is monitored for over- and under-voltage. Under Voltage If the supply voltage VS drops below the switch off voltage VUV OFF, all output transistors are switched off and the power supply fail bit PSF is set. The error is not latched, i.e. if VS rises again and reaches the switch on voltage VUV ON, the power stages are restarted and the error bit is reset. Over Voltage If the supply voltage VS rises above the switch off voltage VOV OFF, all output transistors are switched off and the power supply fail bit (bit 7 of the SPI diagnosis word) is set. The error is not latched, i.e. if VS falls again and reaches the switch on voltage VOV ON, the power stages are restarted and the error is reset.
*
5.1.1
Characteristics Power Supply Monitoring
Electrical Characteristics: Power Supply Monitoring
Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 Parameter UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis OV-Switch-OFF voltage OV-Switch-ON voltage OV-ON/OFF-Hysteresis Symbol Min. Limit Values Typ. - - 0.25 - - 1 Max. 5.2 5.0 - 25 24 - V V V V V V - 4.0 - 21 20 0.5 Unit Conditions
VUVON VUVOFF VUVHY VOVOFF VOVON VOVHY
VS increasing VS decreasing VUVON - VUVOFF VS increasing VS decreasing VOVOFF - VOVON
5.2
Temperature Monitoring
Temperature sensors are integrated in the power stages. The temperature monitoring circuit compares the measured temperature to the warning and shutdown thresholds. If one or more temperature sensors reach the warning temperature, the temperature warning bit TW is set to HIGH. This bit is not latched (i.e. if the temperature falls below the warning threshold (with hysteresis), the TW bit is reset to LOW again). If one or more temperature sensors reach the shut-down temperature, the outputs are shut down as described in the next paragraph and the temperature shut-down bit TSD is set to HIGH. The shutdown is latched (i.e. the output stages remain off and the TSD bit set high until a SRR command is sent or a power-on reset is performed). If one or more temperature sensors reaches the shutdown threshold, all outputs are switched off.
Final Data Sheet
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Rev. 1.0, 2009-02-04
TLE 8203E
Monitoring Functions
5.2.1
Characteristics Temperature Monitoring
Electrical Characteristics: Temperature Monitoring
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, INH = High; all outputs open, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified) Pos. 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 Parameter Thermal warning junction temperature1) Temperature warning hysteresis Thermal shutdown junction temperature1) Temperature shutdown hysteresis Ratio of SD to W temperature
1) 1) 1)
Symbol Min.
Limit Values Typ. 145 30 175 - 30 1.20 Max. 170 - 200 170 - - 120 - 150 120 - 1.05
Unit C K C C K -
Conditions - - - - - -
TjW
TjW
TjSD
Thermal switch-on junction temperature1) TjSO TjSD
TjSD/TjW
1) Not subject to production test, specified by design.
5.3
Current Sense
A current proportional to the output current that flows from the selected power output to GND is provided at the ISO (I sense out) pin. The output selection is done via the SPI. The sense current can be transformed into a voltage by an external sense resistor and provided to an A/D converter input (see Chapter 12).
5.3.1
Characteristics Current Sense
Electrical Characteristics: Current Sense
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. HS4 (Register IS = 011) 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 Output voltage range Current sense ratio Current sense accuracy Output voltage range Current Sense Ratio for HS7 Current Sense accuracy Limit Values Typ. - 1000 - - 2000 - Max. 3 - 10 3 - 10 V - % V - % Unit Conditions
VISO4 kILIS4 kILISacc4 VISO7 kILIS7 kILISacc7
0 - - 0 - -
VDD = 5 V kILIS = IOUT/IISO; IOUT > 1.5 A VDD = 5 V kILIS = IOUT/IISO; IOUT > 2 A
HS7 (Register IS = 100)
Final Data Sheet
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Rev. 1.0, 2009-02-04
TLE 8203E
Power Supply
6
6.1
Power Supply
General
The TLE 8203E has two power domains: All power drivers are connected to the supply voltage VS which is connected to the automotive 12 V board-net. The internal logic part is supplied by a separate Voltage VDD = 5 V. The advantage of this system is that information stored in the logic remains intact in the event of short-term failures in the supply voltage VS. The system can therefore continue to operate after VS has recovered, without having to be reprogrammed. A rising edge on VDD triggers an internal Power-On Reset (POR) to initialize the IC at power-on. All data stored internally is deleted, and the outputs are switched to high-impedance status (tristate).
6.2
Sleep-Mode
The TLE 8203E can be put in a low current-consumption mode by setting the input INH to LOW. The INH pin has an internal pull-down current source. In sleep-mode, all output transistors are turned off and the SPI is not operating. When enabling the IC by setting INH from L to H, a Power-On Reset is performed as described above.
6.3
Reverse Polarity
The TLE 8203E requires an external reverse polarity protection. The gate-driver (charge-pump output) for an external n-channel logic-level MOSFET is integrated. The gate voltage is provided at pin GO which should be connected as shown in the application diagram.
6.4
Electrical Characteristics
Electrical Characteristics: Power Supply
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Current Consumption 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 Supply current Logic supply current Supply quiescent current Logic quiescent current Total quiescent current Limit Values Typ. 1.0 2.5 2.5 0.2 3 Max. 7.0 10 5 1 6 mA mA A A A - SPI not active INH = L; Unit Conditions
IS IDD IS_Q IDD_Q IS_Q + IDD_Q VGO - VS tGO IlkGO
- - - - -
VS = 14 V; VOUTX = 0 V; Tj < 85 C IGO = 50 A
-
Charge Pump-output for Reverse-Polarity Protection FET (GO) 6.4.6 6.4.7 6.4.8 Gate-Voltage Setup-time Reverse leakage current 5 - - - - - 8 1 5 V ms A
VS = 0 V; VGO = -14 V
Final Data Sheet
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Rev. 1.0, 2009-02-04
TLE 8203E
SPI
7
7.1
SPI
General
The SPI is used for bidirectional communication with a control unit. The TLE 8203E acts as SPI-slave and the control unit acts as SPI-master. The 16-bit control word is read via the DI serial data input. The status word appears synchronously at the DO serial data output. The communication is synchronized by the serial clock input CLK. Standard data transfer timing is shown in Figure 3. The clock polarity is data valid on falling edge. CLK must be low during CSN transition. The transfer is MSB first. The transmission cycle begins when the chip is selected with the chip-select-not (CSN) input (H to L). Then the data is clocked through the shift register. The transmission ends when the CSN input changes from L to H and the word which has been read into the shift register becomes the control word. The DO output switches then to tristate status, thereby releasing the DO bus circuit for other uses. The SPI allows to parallel multiple SPI devices by using multiple CSN lines. The SPI can also be used with other SPI-devices in a daisy-chain configuration.
CSN High to Low & rising edge of SCLK: SDO is enabled. Status information is transfered to Output Shift Register CSN CSN Low to High: Data from Shift-Register is transfered to Output Driver Logic CLK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
time
actual Data DI 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
new Data 15 14
SDI: Data will be accepted on the falling edge of CLK-Signal previous Status DO EF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10 actual Status 15 14
SDO: State will change on the rising edge of CLK-Signal
Figure 3
SPI Standard Data Transfer Timing
7.2
Register Address
The 16-bit SPI frame is composed of an addressable block, an address-independent block and a 2-bit address as shown in Figure 4. The control word transmitted from the master to the TLE 8203E is executed at the end of the SPI transmission (CSN L -> H) and remains valid until a different control word is transmitted or a power on reset occurs. At the beginning of the SPI transmission (CSN H -> L), the diagnostic data currently valid are latched into the SPI and transferred to the master. For Status Register address handling, please refer to Section 7.4.
Final Data Sheet
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Rev. 1.0, 2009-02-04
TLE 8203E
SPI
CSN time bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DI
Input data Data for selected register address output data Data from selected register address
generic data
Register Address
DO
generic data
Figure 4
SPI Structure
7.3 7.3.1
Table 1 Bit
SPI Bit Definitions Control - Word
Input (Control) Data Register CtrlReg 01 PWM1 Input Select HS7sel1 HS8sel1 x HS10sel1 x x x x OpL7ON Testmode = 0 IS_2 IS_1 IS_0 SRR RA_1 = 0 RA_0 = 1 CtrlReg 11 CtrlReg 10 Mirror and Lamp-driver PWM2 Input Select Control LS4ON HS4ON LS5ON HS5ON LS6ON HS6ON HS8ON x HS10ON x IS_2 IS_1 IS_0 SRR RA_1 = 1 RA_0 = 0 HS7sel2 HS8sel2 x HS10sel2 x x x x OpL8ON OpL10ON IS_2 IS_1 IS_0 SRR RA_1 = 1 RA_0 = 1
CtrlReg 00 Mirror Heat Control x x x x x x HS7ON Testmode = 0 Testmode = 0 Testmode = 0 IS_2 IS_1 IS_0 SRR RA_1 = 0 RA_0 = 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address - Independent Data
Address - Bits
Note: Testmode is entered when the Testmode bits are set to High. Otherwise set to Low for normal operation.
Final Data Sheet
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Rev. 1.0, 2009-02-04
TLE 8203E
SPI
Table 2 Control Bit LSxON HSxON xsel1 xsel2 OpLxON IS_x
Control Bit Definitions Definition Low-side switch no. x is turned ON (OFF) if this bit is set to HIGH (LOW). High-side switch no. x is turned ON (OFF) if this bit is set to HIGH (LOW). Power switch x is selected to be switched by the PWM1 input. Power switch x is selected to be switched by the PWM2 input The pull-up current for open-load detection on output 4, 5 and 6 are switched on (off) if this bit is set to HIGH (LOW). The output for the current sense multiplexer is selected by these bits: IS_2 0 0 0 0 1 all others IS_1 0 0 1 1 0 IS_0 0 1 0 1 0 Power stage selected for current sense x x x HS4 HS7 no output selected (IISO = 0)
SRR RA_x
Status Register Reset. If set to high, the error bits of the selected status register are reset after transmission of the data in the next SPI frame (see Chapter 7.4). Register Address, selects the control-register address for the current SPI transmission and the status-register address for the next SPI transmission.
7.3.2
Table 3 Bit
Diagnosis
Output (Status) Data Register StatReg 01 Lock and Mirror Heat Open Load valid for input data RA = 01 x x x x x x HS7OpL x x x PSF TSD TW StatReg 10 StatReg 11 Mirror and Lamp-driver Mirror and Lamp-driver Overload Open Load valid for input data RA = 10 LS4OvL HS4OvL LS5OvL HS5OvL LS6OvL HS6OvL HS8OvL x HS10OvL x PSF TSD TW valid for input data RA = 11 LS4OpL x LS5OpL x LS6OpL x HS8OpL x HS10OpL x PSF TSD TW
StatReg 00 Lock and Mirror Heat Overload valid for input data RA = 00
15 14 13 12 11 10 9 8 7 6 5 4 3
x x x x x x HS7OvL x x x PSF TSD TW
Address - Independent Data
Error Flags Final Data Sheet 14 Rev. 1.0, 2009-02-04
TLE 8203E
SPI Table 3 Bit Output (Status) Data Register (cont'd) StatReg 01 Lock and Mirror Heat Open Load EF_11 EF_10 EF_00 StatReg 11 StatReg 10 Mirror and Lamp-driver Mirror and Lamp-driver Open Load Overload EF_11 EF_01 EF_00 EF_10 EF_01 EF_00
StatReg 00 Lock and Mirror Heat Overload EF_11 EF_10 EF_01
2 1 0
Note: x-bits are set to low Table 4 Status Bit LSxOvL HSxOvL LSxOpL HSxOpL PSF TSD TW EF_xy N.C. Status Bit Definitions Definition Low-Side switch Over Load. Set to HIGH if low-side switch no. x is shut down due to overcurrent or overtemperature or crosscurrent. High-Side switch Over Load. Set to HIGH if high-side switch no. x is shut down due to overcurrent or overtemperature or crosscurrent. Low-Side switch open load. Set to HIGH if open load (undercurrent) is detected in low-side switch x. High-Side switch Open Load. Set to HIGH if open load is detected in high-side switch x. Power Supply Fail. Set to HIGH if the Voltage at the VS pin is below the VS undervoltage threshold or above the VS overvoltage threshold. All powerstages are shut down due to overtemperature. One or more powerstages have reached the warning temperature. Error Flag for StatReg xy. Set to HIGH if any bit is set to HIGH StatReg xy. Not connected. These bits may be used for test-mode purposes. They are set to fixed LOW in normal operation.
7.4
Status Register Address Selection and Reset
The SPI is using a standard shift-register concept with daisy-chain capability. Any data transmitted to the SPI will be available to the internal logic part at the end of the SPI transmission (CSN L -> H). To read a specific register, the address of the register is sent by the master to the SPI in a first SPI frame. The data that corresponds to this address is transmitted by the SPI DO during the following (second) SPI frame to the master. The default address for Status Register transmission after Power-ON Reset is 00. The Status-Register-Reset command-bit is executed after the next SPI transmission. The three bits RA_0, RA_1 and SRR act as command to read and reset (or not reset) the addressed Status-Register. This is also explained in Figure 5. The TSD status bit is not part of the addressable data but of the address independent data. When any of the status registers is reset, the TSD bit is reset, too.
Final Data Sheet
15
Rev. 1.0, 2009-02-04
TLE 8203E
SPI
CSN Ctrl-Reg 01 Data Ctrl-Reg 10 Data Ctrl-Reg 11 Data
RA_0 RA_1
RA_1 SRR
RA_0
RA_0 RA_1
SRR
SRR
SI
xxxxx Stat-Reg 00 Data
0
01
xxxxx Stat-Reg 01 Data
1
10
xxxxx Stat-Reg 10 Data
01
1
EF_2
EF_0 EF_1
EF_1 EF_2
EF_0
EF_2
EF_0 EF_1
SO
xxxxx
xx
x
xxxxx
x
xx
xxxxx
xx
x
StatReg10 is reset after CSN L->H
Comment
After Power-ON Reset, Status Register 00 is sent by default
Status Register 01 is transferred to SPI master, but not reset after transmission
Status Register 10 is transferred to SPI master, and reset after transmission
t
Figure 5
Status Register Addressing and Reset
7.4.1
Error-Flag
In addition to the 16 bits transferred from the TLE 8203E to the SPI master, an additional Error Flag (EF) is transmitted at the DO pin. The EF status is shown on the DO pin after CSN H -> L, before the first rising edge at CLK, as shown in Figure 6. The Error flag is set to H if any of the Status Registers contains an error message (i.e. EF = EF_00 or EF_01 or EF_10 or EF_11).
CSN CLK DO Z EF bit15 bit14 bit13 bit12
CSN CLK DO Z EF Z
Figure 6
Error Flag Transmission on DO during Standard SPI Transmission (top), or without Additional SPI Transmission, CLK Low (bottom) 16 Rev. 1.0, 2009-02-04
Final Data Sheet
TLE 8203E
SPI
7.5
Electrical Characteristics
Electrical Characteristics: SPI-Timing
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11 7.5.12 Parameter CSN lead time CSN lag time Fall time for CSN, CLK, DI, DO Rise time for CSN, CLK, DI, DO DI data setup time DI data hold time DI data valid time DO data setup time DO data hold time No-data-time between SPI commands Clock frequency Symbol Min. Limit Values Typ. - - - - - - - - - - - - Max. - - 25 25 - - 50 60 - - 2 60 ns ns ns ns ns ns ns ns ns s MHz %
1) 1) 1) 1) 1) 1) 1) 1) 1) 1)
Unit
Conditions
tlead tlag tf tr tSU th tv tDOsetup tDOhold tnodata fCL
100 100 - - 40 40 - 0 50 5 - 40
1) 1)
Duty cycle of incoming clock at CLK -
1) SPI Timing is not subject to production test - specified by design. SPI functional test is performed at 5 MHz CLK frequency. Timing specified with an external load of 30 pF at pin [DO].
Figure 7
Timing Diagram
7.6
PWM Inputs
The PWM inputs PWM1 and PWM2 are direct power stage control inputs that can be used to switch on and off one or more of the power transistors with a PWM signal supplied to this pin. The setting of the SPI Registers CtrlReg_01 and CtrlReg_11 defines which of the power stages will be controlled by the PWM inputs. If the selection-bits of power Stage x, xsel1 and xsel2 are LOW, the power stage x is controlled only via the SPI control bit xON. If the selection bit xsel1 is HIGH and the control bit xON is also high, the power stage x is controlled by the PWM1 pin (xsel2 and PWM2, respectively). The behavior is shown in the principal schematic and in Table 5 below. In terms of power dissipation due to switching loss, a PWM frequency below 200 Hz is recommended. Final Data Sheet 17 Rev. 1.0, 2009-02-04
TLE 8203E
SPI
CSN DI CLK DO
S P I xsel1 xsel2
xON
x {HS7, HS8, HS10}
PWM1
1
& & &
& Gate driver OUT x
PWM2
1
control logic of power transistor x
power transistor x
Figure 8 Table 5 xON 0 1 1 1 1 1 1 1 1
PWM Input and SPI Control Registers Truth Table for PWM Inputs xsel1 x 0 1 1 0 0 1 1 1 xsel2 x 0 0 0 1 1 1 1 1 PWM1 x x 0 1 x x 1 x 0 PWM2 x x x x 0 1 x 1 0 Power Stage x OFF ON OFF ON OFF ON ON ON OFF
Final Data Sheet
18
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 4-6 (Bridge Outputs)
8
8.1 8.1.1
Power-Outputs 4-6 (Bridge Outputs)
Protection and Diagnosis Short Circuit of Output to Ground or Vs
The low-side switches are protected against short circuit to supply and the high-side switches against short to GND. If a switch is turned on and the current rises above the shutdown threshold ISD for longer than the shutdown delay time tdSD, the output transistor is turned off and the corresponding diagnosis bit is set. During the delay time, the current is limited to ISC as shown in Figure 9.
ISC OUTx short to Vs IOUT ISD tdSD
short to GND
t
Figure 9
Short Circuit Protection
The delay time is relatively short (typ. 25 s) to limit the energy that is dissipated in the device during a short circuit. This scheme allows high peak-currents as required in motor-applications. The output stage stays off and the error bit set until a status register reset is sent to the SPI or a power-on reset is performed.
8.1.2
Cross-Current
If for instance HS4 is ON and LS4 is OFF, you can turn OFF HS4 and turn ON LS4 with the same SPI command. To ensure that there is no overlap of the switching slopes that would lead to a cross current, the dead-time H to L and L to H is specified. In the control registers, it is also possible to turn ON high- and low-side switches of the same half-bridge (e.g. LS4ON = H and HS4ON = H). To prevent a cross-current through the bridge, such a command is not executed. Instead, both switches are turned OFF and the Over-Load bit is set High for both switches (e.g. LS4OvL = H and HS4OvL = H).
8.1.3
Open Load
Open-load detection in ON-state is implemented in the low-side switches of the bridge outputs: When the current through the low side transistor is lower than the reference current IOCD in ON-state for longer than the open-load detection delay time tdOC, the according open-load diagnosis bit is set. The output transistor, however, remains ON. The open load error bit is latched and can be reset by the SPI status register reset or by a power-on reset. As an example, if a motor is connected between outputs OUT 4 and OUT 5 with a broken wire as shown in Figure 10, the resulting diagnostic information is shown in Table 6.
Final Data Sheet
19
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 4-6 (Bridge Outputs)
HS1 LS1
OUT 4 Open Load
Motor HS2 LS2 OUT 5
Figure 10 Table 6
Open Load Example Open Load Diagnosis Example Control Motor Connected Diagnostic Information Motor Remark on Open Load Disconnected Detection LS4 OpL 0 1 0 0 1 LS5 OpL 0 0 1 0 1 not detectable detected detected not detectable not detectable
LS4 ON 0 1 0 0 1
HS4 ON 0 0 1 1 0
LS5 ON 0 0 1 0 1
HS5 ON 0 1 0 1 0
Motor Rotation motor off clock-wise counter clockwise brake high brake low
LS4 OpL 0 0 0 0 1
LS5 OpL 0 0 0 0 1
8.2
Electrical Characteristics
Electrical Characteristics: OUT4 (Driver for mirror xy and halfbridge for fold)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Static Drain-Source ON-Resistance 8.2.1 High- and low-side switch Limit Values Typ. 0.3 0.4 Max. - 0.7 Unit Conditions
RDSON4
- -
IOUT = 1 A; Tj = 25 C IOUT = 1 A Tj = 150 C VS = 14 V;
resistive load of 14 , see Figure 11 and Figure 12
Switching Times 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 High-side ON delay-time High-side OFF delay time Low-side ON delay-time Low-side OFF delay time Dead-time H to L
tdONH4 tdOFFH4 tdONL4 tdOFFL4 tDHL4
20
- - - - 3
50 25 50 25 -
100 50 100 50 -
s s s s s
tdONL4 - tdOFFH4
Rev. 1.0, 2009-02-04
Final Data Sheet
TLE 8203E
Power-Outputs 4-6 (Bridge Outputs) Electrical Characteristics: OUT4 (Driver for mirror xy and halfbridge for fold) (cont'd)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 Parameter Dead-time L to H Over-current shutdown threshold Shutdown delay time Short Circuit current Detection current Delay time OFF-state output current
1)
Symbol Min.
Limit Values Typ. - 4 25 6 25 350 - Max. - 8 50 - 45 600 10 3 3 10 - 12 200
Unit s A s A mA s A
Conditions
tDLH4 ISD4 tdSD4 ISC4 IOCD4 tdOC4
tdONH4 - tdOFFL4
high- and lowside
Short Circuit Protection
Open Load Detection low-side
Leakage Current
IOUT4_leakage -
VOUT = 0.2 V
1) Not subject to production test - specified by design.
Electrical Characteristics: OUT 5, 6 (driver for mirror x-y position)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Static Drain-Source ON-Resistance 8.2.14 High- and low-side switch Limit Values Typ. 0.5 0.8 Max. - 1.3 Un Conditions it
RDSON56
- -
IOUT = 0.5 A; Tj = 25 C IOUT = 0.5 A Tj = 150 C VS = 14 V;
resistive load of 25 , see Figure 11 and Figure 12
Switching Times 8.2.15 8.2.16 8.2.17 8.2.18 8.2.19 8.2.20 8.2.21 8.2.22 8.2.23 8.2.24 8.2.25 High-side ON delay time High-side OFF delay time Low-side ON delay time Low-side OFF delay time Dead-time H to L Dead-time L to H Over-current shutdown threshold Shutdown delay time Short Circuit current Detection current Delay time
1)
tdONH56 tdOFFH56 tdONL56 tdOFFL56 tDHL56 tDLH56 ISD56 tdSD56 ISC56 IOCD56 tdOC56
- - - - 3 3 1.25 10 - 12 200
50 25 50 25 - - 1.5 25 3.0 25 350
100 50 100 50 - - 3.0 50 - 40 600
s s s s s
tdONL56 - tdOFFH56 s tdONH56 - tdOFFL56
A s A mA low-side s high- and low-side
Short Circuit Protection
Open Load Detection
Final Data Sheet
21
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 4-6 (Bridge Outputs) Electrical Characteristics: OUT 5, 6 (driver for mirror x-y position) (cont'd)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Leakage Current 8.2.26 OFF-state output current Limit Values Typ. - Max. 10 Un Conditions it A VOUT = 0.2 V
IOUT56_leakage -
1) Not subject to production test - specified by design.
CSN
ON -> OFF OUTx OFF high-side OFF delay time tdOFFH
10%
tDHL OFF OFF -> ON OUTx tdONL
90%
low-side ON delay time
Figure 11
Timing Bridge Outputs High to Low
CSN
OFF OUTx ON -> OFF
low-side OFF delay time tdOFFL
90%
tDLH OFF -> ON OUTx OFF high-side ON delay time tdONH
10%
Figure 12
Timing Bridge Outputs Low to High
Final Data Sheet
22
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Output 7 (Mirror Heater Driver)
9
9.1 9.1.1
Power-Output 7 (Mirror Heater Driver)
Protection and Diagnosis Short Circuit of Output to Ground
Output 7 is a high-side switch intended to drive ohmic loads like the heater of an exterior mirror.
If the high-side switch is turned on and the current rises above the shutdown threshold ISD for longer than the shutdown delay time tdSD, the output transistor is turned off and the corresponding diagnosis bit is set. During the delay time, the current is limited to ISC as shown in Figure 13.
ISC OUT 7 short to GND IOU T ISD td SD
t
Figure 13
Short Circuit Protection
The output stage stays off and the error bit set until a status register reset is sent to the SPI or a power-on reset is performed.
9.1.2
Open Load
For the high-side switches, an open-load in OFF-state scheme is used as shown in Figure 10. The output is pulled up by a current source IOpL. In OFF-state, the output voltage is monitored and compared to the threshold VOpL. If the voltage rises above this threshold, the open-load signal is set to high. This is equivalent to comparing the load resistance to the value VOpL / IOpL. The open load error bit is latched and can be reset by the SPI status register reset or by a power-on reset. The pull-up current can be switched on and off by the OpLxON bits. This bit should be set to LOW (i.e. pull-up current switched off) if an output is used to drive LEDs because they may emit light if biased with the pull-up current.
Final Data Sheet
23
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Output 7 (Mirror Heater Driver)
OpL7ON
IOpL
switch ON HS7
Gate driver high-side switch 7 + VOpL + -
OUT 7
1 HS7OpL Filter &
RLoad
Figure 14
Open Load in OFF-state Scheme
9.2
Electrical Characteristics
Electrical Characteristics: OUT 7(mirror heater driver)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Static Drain-source ON-Resistance 9.2.1 High-side switch Limit Values Typ. 0.07 0.1 Max. - 0.17 Unit Conditions
RDSON7
- -
IOUT = 2.5 A; Tj = 25 C IOUT = 2.5 A Tj = 150 C VS = 14 V;
resistive load of 10 , see Figure 15
Switching Times 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 Turn-ON delay time Output rise-time Turn-OFF delay time Output fall-time Over-current shutdown threshold Shutdown delay time Short Circuit current Pull-up current
1)
tdONH7 trise7 tdOFFH7 tfall7 ISD7 tdSD7 ISC7 IOpL7
24
- - - - 6.25 10 - 100
5 15 20 5 8 25 12 -
15 40 40 10 11 50 - 300
s s s s A s A A
Short Circuit Protection - - -
Open Load Detection
VOUT = 4 V
Rev. 1.0, 2009-02-04
Final Data Sheet
TLE 8203E
Power-Output 7 (Mirror Heater Driver) Electrical Characteristics: OUT 7(mirror heater driver) (cont'd)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 9.2.10 9.2.11 9.2.12 Parameter Detection Threshold Delay time OFF-state output current Symbol Min. Limit Values Typ. - - - Max. 4 200 5 V s A - - 2 - Unit Conditions
VOpL7 tdOC7
Leakage Current
IOUT7_leakage -
VOUT = GND
1) Not subject to production test - specified by design.
PWM tRISE
90% 90%
PWM
t FALL
OUT7 t dON
10%
t dOFF
10%
Figure 15
Timing OUT 7
Final Data Sheet
25
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 8 and 10 (Lamp drivers)
10
10.1 10.1.1
Power-Outputs 8 and 10 (Lamp drivers)
Protection and Diagnosis Short Circuit of Output to Ground
Outputs 8 and 10 are a high-side switches intended to drive ohmic loads 5 W or 10 W lamp (bulb) loads.
The high-side switches Out 8 and 10 are protected against short to GND. Short Circuit during Switch-on During switch-on of an output a current and voltage level is used to check for a short circuit. If a switch is turned on and the short circuit condition is valid after tdSDon8 the output transistor is turned off and the corresponding diagnosis bit is set. A short circuit condition is valid if the current rises above the shutdown threshold ISD8 and the voltage at the output stays below VSD8. During the delay time, the current is limited to ISC8 as shown in Figure 16
OUT 8, 10 IOUT short to GND VOUT IOUT
ISC8 ISD8 tdSDon8
t VSD8 VOUT
Figure 16
Short Circuit Protection during Switch-on
Final Data Sheet
26
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 8 and 10 (Lamp drivers) Short Circuit in On-state If a switch is already on and the current rises above the shutdown threshold ISD for longer than the shutdown delay time tdSD the output transistor is turned off and the corresponding diagnosis bit is set. This is independent of the voltage Vout. See Figure 17.
OUT 8, 10 IOUT short to GND IOUT
ISC8 ISD8 tdSD8
t
Figure 17
Short Circuit Protection in On-state
10.1.2
Open Load
For the high-side switches, an open-load in OFF-state scheme is used as shown in Figure 18. The output is pulled up by a current source IOpL. In OFF-state, the output voltage is monitored and compared to the threshold VOpL. If the voltage rises above this threshold, the open-load signal is set to high. This is equivalent to comparing the load resistance to the value VOpL / IOpL. The open load error bit is latched and can be reset by the SPI status register reset or by a power-on reset. The pull-up current can be switched on and off by the OpLxON bits. This bit should be set to LOW (i.e. pull-up current switched off) if an output is used to drive LEDs because they may emit light if biased with the pull-up current.
OpLxON
IOpL
switch ON HSx
Gate driver 1 high-side switch + V OpL + -
OUT x
HSxOpL
Filter
&
R Load
Figure 18
Open Load in OFF-state Scheme 27 Rev. 1.0, 2009-02-04
Final Data Sheet
TLE 8203E
Power-Outputs 8 and 10 (Lamp drivers)
10.2
Electrical Characteristics
Electrical Characteristics: OUT 8, 10 (Lamp drivers)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Static Drain-Source ON-Resistance 10.2.1 High-side switch Limit Values Typ. 0.4 0.5 Max. - 0.8 Unit Conditions
RDSON8,10
- -
IOUT = +0.5 A; Tj = 25 C IOUT = +0.5 A Tj = 150 C VS = 14 V;
resistive load of 25 , see Figure 15
Switching Times 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.2.8 10.2.9 Turn-ON delay time Output rise-time Turn-OFF delay time Output fall-time Over-current shutdown threshold Over-current shutdown threshold voltage Short circuit current1) Shutdown delay time
tdONH8,10 trise8,10 tdOFFH8,10 tfall8,10 ISD8,10 VSD8,10 ISC8,10 tdSDon8,10 tdSD8,10 IOpL8,10 VOpL8,10 tdOC8,10
- 5 - 7 1.8 1.5 - 125 10 100 2 -
5 10 25 15 2.9 2.5 4.2 200 25 - - - -
15 30 50 30 3.5 3.3 - 350 60 250 4 200 5
s s s s A V A s s A V s A
Short Circuit Protection - - - at switching-on in on-state
10.2.10 Shutdown delay time Open Load Detection 10.2.11 Pull-up current 10.2.12 Detection Threshold 10.2.13 Delay time Leakage Current 10.2.14 OFF-state output current
VOUT = 4 V
- -
IOUT810_leakage -
VOUT = GND
1) Not subject to production test - specified by design.
PWM tRISE
90% 90%
PWM
t FALL
OUT 8, 10 t dON
10%
t dOFF
10%
Figure 19
Timing OUT 8, 10 28 Rev. 1.0, 2009-02-04
Final Data Sheet
TLE 8203E
Logic In- and Outputs
11
Logic In- and Outputs
The threshold specifications of the logic inputs are compatible to both 5 V and 3.3 V standard CMOS micro controller outputs. The logic output DO is a 5 V CMOS output.
11.1
Electrical Characteristics
Electrical Characteristics: Diagnostics
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 C to +150 C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Inhibit Input 11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 11.1.6 11.1.7 11.1.8 11.1.9 H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull-down current H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull-up current at pin CSN Pull-down current at pins PWM1, PWM2, DI, CLK Limit Values Typ. - - - - - - - -25 25 10 Max. 2 - 600 50 2 - 600 -10 50 15 V V mV A V V mV A A pF Unit Conditions
VIH VIL VIHY IIINH VIH VIL VIHY IICSN IInput CI
- 1 100 - - 1 100 -50 10 -
VIN rising VIN falling
-
VIINH = 2 V VIN rising VIN falling
-
Logic Inputs DI, CLK, CSN, PWM1 and PWM2
VCSN = 1 V VInput = 2 V
0 V < VDD < 5.25 V
11.1.10 Input capacitance at pin CSN, DI, CLK, PWM1, PWM21) Logic Output DO 11.1.11 H-output voltage level 11.1.12 L-output voltage level 11.1.13 Tri-state leakage current 11.1.14 Tri-state input capacitance1)
VDOH VDOL IDOLK CDO
VDD 1.0 - -10 -
VDD 0.7 0.2 - 10
- 0.4 10 15
V V A pF
ISDOH = 1 mA ISDOL = -1.6 mA VCSN = VDD; 0 V < VSDO < VDD VCSN = VDD; 0 V < VDD < 5.25 V
1) Not subject to production test, specified by design.
Final Data Sheet
29
Rev. 1.0, 2009-02-04
TLE 8203E
Application Information
12
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.
12.1
Application Diagram
VBATT_1
22 F 220 pF 100 nF
VS
TLE 8458
VBATT_2
10 F 100 nF 100k
V CC
IPD 30N03S2L-07
LIN
47uF // 2 x 100 nF
< 40V
3.3nF
LIN
EN TxD RxD
WK
GND
GO
RxD VDD TxD GPIO 3
Vs
CP
VDD
XC866
INH CSN CLK DI DO PWM1 PWM2 ISO Rsense 700
TLE 8203 E
OUT 4 GPIO 1 GPIO 2 SCLK SDI SDO TIMER 1 TIMER 2 A/D mirror-x M OUT 5 mirror-y OUT 6
M
OUT 7 mirror-heat
OUT 8 OUT 10
DIG_GND
POWER_GND
Figure 20
Application Example for Mirror Control
Final Data Sheet
30
Rev. 1.0, 2009-02-04
TLE 8203E
Package Outlines
13
Package Outlines
0...0.10 STAND OFF 2.45 -0.2
2.55 MAX.
3)
0.35 x 45
0.65 C 17 x 0.65 = 11.05 0.33 0.08 2) 0.17 A
36 19 M
1.1
0.7 0.2 0.1 C 36x SEATING PLANE 10.3 0.3 D
A-B C D 36x
Bottom View
19 36
Ejector Mark
Exposed Diepad
Y
1
18
18
B 12.8 -0.21) Index Marking
X
1
Index Marking
Exposed Diepad Dimensions Leadframe Package PG-DSO-36-24, -41, -42 A6901-C001 A6901-C003 PG-DSO-36-38 A6901-C007 PG-DSO-36-38 PG-DSO-36-50 A6901-C008
X 7 7 5.2 6.0
Y 5.1 5.1 4.6 5.4
1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side 3) Distance from leads bottom (= seating plane) to exposed diepad
PG-DSO-36-24, -38, -41, -42, -50-PO V09
Figure 21
PG-DSO-36-50 (Plastic Dual Small Outline Package)
Green Product ( RoHS compliant ) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Final Data Sheet 31
Dimensions in mm Rev. 1.0, 2009-02-04
8 MAX.
7.6 -0.2 1)
0.23 +0.09
TLE 8203E
Revision History
14
0.9
Revision History
Date 03.02.09 Changes Final Data Sheet Release
Version 1.0
Final Data Sheet
32
Rev. 1.0, 2009-02-04
Edition 2009-02-04 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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